integrated circuit systems, inc. general description features ics9147-06 block diagram pentium is a trademark of intel corporation frequency generator & integrated buffers for pentium tm 9147- 06 reva 5/29/97p pin configuration the ics9147-06 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro. two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. glitch-free stop clock control is provided for cpu and bus clocks. complete chip low current mode is achieved with the power down# pin. high drive bus outputs typically provide greater than 1 v/ ns slew rate into 30 pf loads. cpu outputs typically provide better than 1v/ns slew rate into 20 pf loads while maintaining 50 5% duty cycle. the ref and ioapic clock outputs typically provide better than 0.5v/ns slew rates. separate buffer supply pins vddl allow for nominal 3.3v voltage or reduced voltage swing (from 2.9 to 2.5v) for cpu (1:4) and ioapic outputs. ? generates five processor, eight bus, four 14.31818 mhz, two 48 mhz clocks for usb support and one 24 mhz clock. ? cpu to bus clock skew 1 to 4ns (cpu early) ? synchronous clocks skew matched to 250ps window on cpu and 500ps window on bus. ? selectable multiplying ratios ? glitch free stop clock controls cpuen and busen ? 3.0v ? 3.7v supply range, 2.5v to vdd supply range for cpu (1:4) clocks and ioapic clock. ? 48-pin ssop package 48-pin ssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9147-06 pin descriptions functionality pd# busen cpuen fs1 fs0 cpu (1:4) cpuh bus ref ioapic 24 (mhz) 48 (mhz) 11100tris tate tristate tristate tristate tristate 11101603014. 31818 24 48 1111066.633.314. 31818 24 48 11111ref/2ref/4refref/4ref/2 1 1 0 x x low running 14.31818 24 48 1 0 1 x x running low 14.31818 24 48 0 xxxxlowlowlowlowlow pin number pin name type description 1, 2, 47 ref1, ref2, ref3 out 14.318 mhz reference clock outputs. 3, 10, 18, 24, 30, 32, 37, 43, 44 gnd pwr ground. 4x1 in crystal input, has internal crystal load capacitor, and feedback resistor from x2. nominally 14.31818mhz. 5 x2 out crystal output, has internal crystal load capacitor 8, 9, 11, 12, 13, 14, 16, 17 bus (1:8) out bus clock outputs, operates synchronously at cpu/2. 26, 27 fs (0:1) in select pin for enabling cpu and bus clock frequencies.* 7, 15, 21, 25, 34, 48 vdd3 pwr core and buffer output clock power supply. 22, 23 48m (1:2) out 48 mhz clock output 28 pd# i n device power down input, stops outputs low and shuts off crystal oscillator and plls when low.* 29 cpuen i n output enable for all cpu clocks, a logic low will stop low all cpu clocks.* 36 cpuh out 3.3 (vdd3 dependent) cpu clock output 38, 39, 41, 42 cpu (1:4) out cpu clock output clocks, operates at vddl supply voltage (with ioapic), either nominal 3.3v vdd or reduced voltage 2.9 to 2.5v. 6busen in output enable for all bus clock, a logic low will stop low all bus clocks.* 45 ioapic out ioapic clock output. (14.318 mhz), operates at vddl supply voltage with cpu (1:4), either nominal 3.3v vdd or reduced voltage 2.9 to 2.5v. 40, 46 vddl pwr power supply for cpu and ioapic block buffers, operates at nominal 3.3v vdd or reduced voltage 2.9 to 2.5v. 33 24m out 24 mhz clock output * has internal pull-up to v dd3 .
3 ics9147-06 absolute maximum ratings electrical characteristics at 3.3v supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating t emperature . . . . . . . . . . 0c to +70c storage t emperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2vdd v input high voltage v ih 0.7v dd --v input low current i il vin=0v -28.0 -10.5 - a input high current i ih vin=vdd -5.0 - 5.0 a output low current i ol1 vol=0.8v; for cpuh, bus & ref1 (and cpu & ioapic at vddl= 3.0 to 3.7v) - 33.0 - ma output high current i oh1 voh=2.0v; for cpuh, bus & ref1 (and cpu & ioapic at vddl = 3.0 to 3.7v) --28.0- ma output low current i ol2 vol=0.8v; ref (2:3), 24, 48 clks - 26.0 - ma output high current i oh2 voh=2.0v; ref (2:3), 24, 48 clks - -21.0 - ma output low current i ol3 vol=0.8v; for cpul at vddl = 2.5v -26-ma output high current i oh3 voh = 1.7v; for cpul at vddl = 2.5v -24-ma output low voltage v ol1 iol = 10ma; for cpuh, bus & ref1 (and cpul at vddl = 3.0 to 3.7v) - 0.22 0.4 v output high voltage v oh1 ioh = -10ma; for cpuh, bus & ref (and cpul at vddl = 3.0 to 3.7v) 2.4 2.8 - v output low voltage v ol2 iol = 8ma - 0.25 0.4 v output high voltage v oh2 ioh = -8ma 2.4 2.6 - v output low voltage v ol3 iol = 8 ma; for cpul at vddl = 2.5v - 0.25 0.4 v output high voltage v oh3 ioh = -8ma; for cpul at vddl = 2.5v 2.1 2.25 - v supply current i dd @66.6 mhz; all outputs unloaded - 70 140 ma supply current i dd pd# 230 500 a v ddl =v dd3 =3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated
4 ics9147-06 electrical characteristics at 3.3v note 1: parameter is guaranteed by design and characterization. not 100% tested in production. v ddl =v dd3 =3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v cpu, bus & ref1 -0.91.5ns fall time 1 t f1 20pf load, 2.0 to 0.8v cpu, bus & ref1 - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80% cpu, bus & ref1 -1.52.5ns fall time 1 t f2 20pf load, 80% to 20% cpu, bus & ref1 - 1.4 2.4 ns rise time 1 t r1 30pf load, 0.8 to 2.0v cpu, bus & ref1 -0.91.5ns fall time 1 t f1 30pf load, 2.0 to 0.8v cpu, bus & ref1 - 0.8 1.4 ns rise time 1 t r2 30pf load, 20% to 80% cpu, bus & ref1 -1.52.5ns fall time 1 t f2 30pf load, 80% to 20% cpu, bus & ref1 - 1.4 2.4 ns rise time 1 t r3 20pf load, 0.8 to 2.0v 24 & 48 clocks & ref (2:3) --- ns fall time 1 t f3 20pf load, 2.0 to 0.8v 24 & 48 clocks & ref (2:3) -- ns rise time 1 t r4 20pf load, 0.4 to 2.0v , cpu with vddl = 2.5v and ioapic - - 1.6 ns fall time 1 t f4 20pf load, 2.0 to 0.4v, cpu with vddl = 2.5v and ioapic - - 1.6 ns duty cycle 1 d t1 20pf load @ vout=1.4v 45 50 55 % duty cycle d t2 ref (1:3) 40 45 50 % jitter, one sigma 1 t jis1 cpu & fixed bus load=20pf, bus; load = 30pf - 50 150 ps jitter, absolute 1 t jab1 cpu & fixed bus load=20pf, bus; load = 30pf -250 - 250 ps jitter, one sigma 1 t jis2 ref1; load = 47pf - 55 250 ps jitter, absolute 1 t jab2 ref1; load = 47pf -500 200 500 ps input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf oscillator input capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from vdd=3.0v to 1st crossing of 66.6 mhz vdd supply ramp < 1 ms -1.53.0 ms clock skew 1 t sk1 cpu to cpu; load=20pf; @1.4v (same vdd) - 150 250 ps clock skew 1 t sk2 bus to bus; load=20pf; @1.4v - 300 500 ps clock skew 1 t sk3 cpu to bus; load=20pf; @1.4v (cpu is early) (all at 3.3v) 13.3 4 ns clock skew 1 t sk4 cpu @ 2.5 to cpuh @ 3.3v t sk5 cpu @ 2.5v to bus @ 3.3v t sk6 ref @ 3.3v to ioapic @ 2.5v
5 ics9147-06 recommended pcb layout for ics9147-06 note: this pcb layout is based on a 4 layer board with an internal ground (common) and vcc plane. placement of components will depend on routing of signal trace. the 0.1uf capacitors should be placed as close as possible to the power pins. placement on the backside of the board is also possible. the ferrite beads can be replaced with 10-15ohm resistors. for best results, use a fixed voltage regulator between the main (board) vcc and the different vdd planes.
6 ics9147-06 ordering information ICS9147F-06 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics = standard device example: ics xxxx f - ppp ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c .005 - .010 d see variations e .292 .296 .299 e 0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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